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 * This software/firmware and related documentation ("AutoChips Software") are
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/*!
 * @file ac780x_ckgen.h
 *
 * @brief This file provides clock generator module integration functions interfaces.
 *
 */

#ifndef _AC780X_CKGEN_H
#define _AC780X_CKGEN_H

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

/* ===========================================  Includes  =========================================== */
#include "ac7803x.h"

/* ============================================  Define  ============================================ */

/* ===========================================  Typedef  ============================================ */
/*!
 * @brief Clock module index enumeration.
 */
typedef enum
{
    /* PERI_CLK_EN_0 */
    CLK_UART0 = 0U,
    CLK_UART1,
    CLK_UART2,
    CLK_RESERVE3,
    CLK_RESERVE4,
    CLK_RESERVE5,
    CLK_SPI0,
    CLK_SPI1,
    CLK_I2C0,
    CLK_I2C1,
    CLK_PWDT0,
    CLK_PWM0,
    CLK_PWM1,
    CLK_PWM2,
    CLK_RESERVE14,
    CLK_RESERVE15,
    CLK_RESERVE16,
    CLK_RESERVE17,
    CLK_RESERVE18,
    CLK_TIMER,
    CLK_RTC,
    CLK_DMA0,
    CLK_RESERVE22,
    CLK_GPIO,
    CLK_RESERVE24,
    CLK_WDG,
    CLK_CRC,
    CLK_EIO,
    CLK_CAN0,
    CLK_CAN1,
    CLK_RESERVE30,
    CLK_RESERVE31,

    /* PERI_CLK_EN_1 */
    CLK_RESERVE32 = 32U,
    CLK_CTU,
    CLK_ADC0,
    CLK_ACMP0,
    CLK_RESERVE36,
    CLK_PWDT1,
    CLK_MODULE_NUM
} CKGEN_ClockType;

#define IS_CKGEN_CLOCK_PARA(CLOCK) (((CLOCK) == CLK_UART0) || \
                                    ((CLOCK) == CLK_UART1) || \
                                    ((CLOCK) == CLK_UART2) || \
                                    ((CLOCK) == CLK_SPI0)  || \
                                    ((CLOCK) == CLK_SPI1)  || \
                                    ((CLOCK) == CLK_I2C0)  || \
                                    ((CLOCK) == CLK_I2C1)  || \
                                    ((CLOCK) == CLK_PWDT0) || \
                                    ((CLOCK) == CLK_PWM0)  || \
                                    ((CLOCK) == CLK_PWM1)  || \
                                    ((CLOCK) == CLK_PWM2)  || \
                                    ((CLOCK) == CLK_TIMER) || \
                                    ((CLOCK) == CLK_RTC)   || \
                                    ((CLOCK) == CLK_DMA0)  || \
                                    ((CLOCK) == CLK_GPIO)  || \
                                    ((CLOCK) == CLK_WDG)   || \
                                    ((CLOCK) == CLK_CRC)   || \
                                    ((CLOCK) == CLK_EIO)   || \
                                    ((CLOCK) == CLK_CAN0)  || \
                                    ((CLOCK) == CLK_CAN1)  || \
                                    ((CLOCK) == CLK_CTU)   || \
                                    ((CLOCK) == CLK_ADC0)  || \
                                    ((CLOCK) == CLK_ACMP0) || \
                                    ((CLOCK) == CLK_PWDT1))

/*!
 * @brief Soft reset module index enumeration.
 */
typedef enum
{
    /* PERI_SFT_RST1 */
    SRST_UART0 = 0U,
    SRST_UART1,
    SRST_UART2,
    SRST_RESERVE3,
    SRST_RESERVE4,
    SRST_RESERVE5,
    SRST_SPI0,
    SRST_SPI1,
    SRST_I2C0,
    SRST_I2C1,
    SRST_PWDT0,
    SRST_PWM0,
    SRST_PWM1,
    SRST_PWM2,
    SRST_RESERVE14,
    SRST_RESERVE15,
    SRST_RESERVE16,
    SRST_RESERVE17,
    SRST_RESERVE18,
    SRST_TIMER,
    SRST_RTC,
    SRST_DMA0,
    SRST_RESERVE22,
    SRST_GPIO,
    SRST_RESERVE24,
    SRST_WDG,
    SRST_CRC,
    SRST_EIO,
    SRST_CAN0,
    SRST_CAN1,
    SRST_RESERVE30,
    SRST_RESERVE31,

    /* PERI_SFT_RST2 */
    SRST_RESERVE32 = 32U,
    SRST_CTU,
    SRST_ADC0,
    SRST_ACMP0,
    SRST_ANA_REG,
    SRST_PWDT1,
    SRST_MODULE_NUM
} CKGEN_SoftResetType;

#define IS_CKGEN_SOFT_RESET_PARA(RESET) (((RESET) == SRST_UART0) || \
                                         ((RESET) == SRST_UART1) || \
                                         ((RESET) == SRST_UART2) || \
                                         ((RESET) == SRST_SPI0)  || \
                                         ((RESET) == SRST_SPI1)  || \
                                         ((RESET) == SRST_I2C0)  || \
                                         ((RESET) == SRST_I2C1)  || \
                                         ((RESET) == SRST_PWDT0) || \
                                         ((RESET) == SRST_PWM0)  || \
                                         ((RESET) == SRST_PWM1)  || \
                                         ((RESET) == SRST_PWM2)  || \
                                         ((RESET) == SRST_TIMER) || \
                                         ((RESET) == SRST_RTC)   || \
                                         ((RESET) == SRST_DMA0)  || \
                                         ((RESET) == SRST_GPIO)  || \
                                         ((RESET) == SRST_WDG)   || \
                                         ((RESET) == SRST_CRC)   || \
                                         ((RESET) == SRST_EIO)   || \
                                         ((RESET) == SRST_CAN0)  || \
                                         ((RESET) == SRST_CAN1)  || \
                                         ((RESET) == SRST_CTU)   || \
                                         ((RESET) == SRST_ADC0)  || \
                                         ((RESET) == SRST_ACMP0) || \
                                         ((RESET) == SRST_PWDT1))

/*!
 * @brief System clock source enumeration.
 */
typedef enum
{
    SYSCLK_SRC_INTERNAL_OSC = 0U,
    SYSCLK_SRC_PLL_OUTPUT,
    SYSCLK_SRC_EXTERNAL_OSC
} SYSTEM_ClockSourceType;

#define IS_CLOCK_SOURCE_PARA(SYSCLK) (((SYSCLK) == SYSCLK_SRC_INTERNAL_OSC) || \
                                      ((SYSCLK) == SYSCLK_SRC_PLL_OUTPUT)   || \
                                      ((SYSCLK) == SYSCLK_SRC_EXTERNAL_OSC))

/*!
 * @brief System clock divide enumeration.
 */
typedef enum
{
    SYSCLK_DIVIDER_1 = 0U,
    SYSCLK_DIVIDER_2,
    SYSCLK_DIVIDER_3,
    SYSCLK_DIVIDER_4
} SYSCLK_DividerType;

#define IS_SYSCLK_DIVIDER_PARA(DIVIDER) (((DIVIDER) == SYSCLK_DIVIDER_1) || \
                                         ((DIVIDER) == SYSCLK_DIVIDER_2) || \
                                         ((DIVIDER) == SYSCLK_DIVIDER_3) || \
                                         ((DIVIDER) == SYSCLK_DIVIDER_4))

/*!
 * @brief APBCLK clock divider enumeration.
 */
typedef enum
{
    APBCLK_DIVIDER_1 = 0U,
    APBCLK_DIVIDER_2,
    APBCLK_DIVIDER_3,
    APBCLK_DIVIDER_4
} APBCLK_DividerType;

#define IS_APBCLK_DIVIDER_PARA(DIVIDER) (((DIVIDER) == APBCLK_DIVIDER_1) || \
                                         ((DIVIDER) == APBCLK_DIVIDER_2) || \
                                         ((DIVIDER) == APBCLK_DIVIDER_3) || \
                                         ((DIVIDER) == APBCLK_DIVIDER_4))

/*!
 * @brief PLL Post divider enumeration.
 */
typedef enum
{
    PLL_POSDIV_2 = 1U,
    PLL_POSDIV_4 = 2U,
    PLL_POSDIV_6 = 3U,
    PLL_POSDIV_8 = 4U,
    PLL_POSDIV_10 = 5U,
    PLL_POSDIV_12 = 6U,
    PLL_POSDIV_14 = 7U,
    PLL_POSDIV_16 = 8U,
    PLL_POSDIV_18 = 9U,
    PLL_POSDIV_20 = 10U,
    PLL_POSDIV_22 = 11U,
    PLL_POSDIV_24 = 12U,
    PLL_POSDIV_26 = 13U,
    PLL_POSDIV_28 = 14U,
    PLL_POSDIV_30 = 15U,
    PLL_POSDIV_32 = 16U,
    PLL_POSDIV_34 = 17U,
    PLL_POSDIV_36 = 18U,
    PLL_POSDIV_38 = 19U,
    PLL_POSDIV_40 = 20U,
    PLL_POSDIV_42 = 21U,
    PLL_POSDIV_44 = 22U,
    PLL_POSDIV_46 = 23U,
    PLL_POSDIV_48 = 24U,
    PLL_POSDIV_50 = 25U,
    PLL_POSDIV_52 = 26U,
    PLL_POSDIV_54 = 27U,
    PLL_POSDIV_56 = 28U,
    PLL_POSDIV_58 = 29U,
    PLL_POSDIV_60 = 30U,
    PLL_POSDIV_62 = 31U
} PLL_PosDivType;

#define IS_PLL_POSDIV_PARA(POSDIV) (((POSDIV) == PLL_POSDIV_2) || \
                                    ((POSDIV) == PLL_POSDIV_4) || \
                                    ((POSDIV) == PLL_POSDIV_6) || \
                                    ((POSDIV) == PLL_POSDIV_8) || \
                                    ((POSDIV) == PLL_POSDIV_10)|| \
                                    ((POSDIV) == PLL_POSDIV_12)|| \
                                    ((POSDIV) == PLL_POSDIV_14)|| \
                                    ((POSDIV) == PLL_POSDIV_16)|| \
                                    ((POSDIV) == PLL_POSDIV_18)|| \
                                    ((POSDIV) == PLL_POSDIV_20)|| \
                                    ((POSDIV) == PLL_POSDIV_22)|| \
                                    ((POSDIV) == PLL_POSDIV_24)|| \
                                    ((POSDIV) == PLL_POSDIV_26)|| \
                                    ((POSDIV) == PLL_POSDIV_28)|| \
                                    ((POSDIV) == PLL_POSDIV_30)|| \
                                    ((POSDIV) == PLL_POSDIV_32)|| \
                                    ((POSDIV) == PLL_POSDIV_34)|| \
                                    ((POSDIV) == PLL_POSDIV_36)|| \
                                    ((POSDIV) == PLL_POSDIV_38)|| \
                                    ((POSDIV) == PLL_POSDIV_40)|| \
                                    ((POSDIV) == PLL_POSDIV_42)|| \
                                    ((POSDIV) == PLL_POSDIV_44)|| \
                                    ((POSDIV) == PLL_POSDIV_46)|| \
                                    ((POSDIV) == PLL_POSDIV_48)|| \
                                    ((POSDIV) == PLL_POSDIV_50)|| \
                                    ((POSDIV) == PLL_POSDIV_52)|| \
                                    ((POSDIV) == PLL_POSDIV_54)|| \
                                    ((POSDIV) == PLL_POSDIV_56)|| \
                                    ((POSDIV) == PLL_POSDIV_58)|| \
                                    ((POSDIV) == PLL_POSDIV_60)|| \
                                    ((POSDIV) == PLL_POSDIV_62))

/*!
 * @brief PLL Previous divider enumeration.
 */
typedef enum
{
    PLL_PREDIV_1 = 0U,
    PLL_PREDIV_2 = 1U,
    PLL_PREDIV_4 = 3U
} PLL_PreDivType;

#define IS_PLL_PREDIV_PARA(PREDIV) (((PREDIV) == PLL_PREDIV_1) || \
                                    ((PREDIV) == PLL_PREDIV_2) || \
                                    ((PREDIV) == PLL_PREDIV_4))

/*!
 * @brief PLL Reference enumeration.
 */
typedef enum
{
    PLL_REF_INTERNAL_OSC = 0U,
    PLL_REF_EXTERNAL_OSC
} PLL_ReferenceType;

#define IS_PLL_REFERENCE_PARA(REF) (((REF) == PLL_REF_INTERNAL_OSC) || \
                                    ((REF) == PLL_REF_EXTERNAL_OSC))

/*!
 * @brief CAN clock source enumeration.
 */
typedef enum
{
    CAN_CLK_SEL_EXTERNAL_OSC = 0U,
    CAN_CLK_SEL_AHB
} CAN_ClockSelectType;

#define IS_CAN_CLOCK_SELECT_PARA(CLOCK) (((CLOCK) == CAN_CLK_SEL_EXTERNAL_OSC) || \
                                         ((CLOCK) == CAN_CLK_SEL_AHB))

/*!
 * @brief CAN time stamp clock divider enumeration.
 */
typedef enum
{
    CAN_TIME_CLK_DIVIDER_8 = 0U,
    CAN_TIME_CLK_DIVIDER_16,
    CAN_TIME_CLK_DIVIDER_24,
    CAN_TIME_CLK_DIVIDER_48
} CAN_TimeClockDividerType;

#define IS_CAN_TIMECLOCK_DIVIDER_PARA(DIVIDER) (((DIVIDER) == CAN_TIME_CLK_DIVIDER_8)  || \
                                                ((DIVIDER) == CAN_TIME_CLK_DIVIDER_16) || \
                                                ((DIVIDER) == CAN_TIME_CLK_DIVIDER_24) || \
                                                ((DIVIDER) == CAN_TIME_CLK_DIVIDER_48))

/*!
 * @brief Clock out select enumeration.
 */
typedef enum
{
    CKGEN_CLKOUT_SEL_HSI = 0U,
    CKGEN_CLKOUT_SEL_HSE,
    CKGEN_CLKOUT_SEL_PLL,
    CKGEN_CLKOUT_SEL_SYS
} CKGEN_ClkOutSelType;

#define IS_CLKOUT_SEL_PARA(SEL) (((SEL) == CKGEN_CLKOUT_SEL_HSI) || \
                                 ((SEL) == CKGEN_CLKOUT_SEL_HSE) || \
                                 ((SEL) == CKGEN_CLKOUT_SEL_PLL) || \
                                 ((SEL) == CKGEN_CLKOUT_SEL_SYS))

/*!
 * @brief Clock out divider enumeration.
 */
typedef enum
{
    CKGEN_CLKOUT_DIV_1 = 0U,
    CKGEN_CLKOUT_DIV_2,
    CKGEN_CLKOUT_DIV_4,
    CKGEN_CLKOUT_DIV_8
} CKGEN_ClkOutDivType;

#define IS_CLKOUT_DIV_PARA(DIV) (((DIV) == CKGEN_CLKOUT_DIV_1) || \
                                 ((DIV) == CKGEN_CLKOUT_DIV_2) || \
                                 ((DIV) == CKGEN_CLKOUT_DIV_4) || \
                                 ((DIV) == CKGEN_CLKOUT_DIV_8))

/* ==========================================  Variables  =========================================== */

/* ====================================  Functions declaration  ===================================== */
/*!
 * @brief Enale the module clock.
 *
 * @param[in] module: CKGEN_ClockType, value can be
 *                   - CLK_UART0
 *                   - CLK_UART1
 *                   - CLK_UART2
 *                   - CLK_SPI0
 *                   - CLK_SPI1
 *                   - CLK_I2C0
 *                   - CLK_I2C1
 *                   - CLK_PWDT0
 *                   - CLK_PWM0
 *                   - CLK_PWM1
 *                   - CLK_PWM2
 *                   - CLK_TIMER
 *                   - CLK_RTC
 *                   - CLK_DMA0
 *                   - CLK_GPIO
 *                   - CLK_WDG
 *                   - CLK_CRC
 *                   - CLK_EIO
 *                   - CLK_CAN0
 *                   - CLK_CAN1
 *                   - CLK_CTU
 *                   - CLK_ADC0
 *                   - CLK_ACMP0
 *                   - CLK_PWDT1
 * @param[in] enable: enable state
 *                   - ENABLE
 *                   - DISABLE
 * @return none
 */
void CKGEN_Enable(CKGEN_ClockType module, ACTION_Type enable);

/*!
 * @brief Do soft reset for the module.
 *
 * @param[in] module: the module to do soft reset, value can be
 *                   - SRST_UART0
 *                   - SRST_UART1
 *                   - SRST_UART2
 *                   - SRST_SPI0
 *                   - SRST_SPI1
 *                   - SRST_I2C0
 *                   - SRST_I2C1
 *                   - SRST_PWDT0
 *                   - SRST_PWM0
 *                   - SRST_PWM1
 *                   - SRST_PWM2
 *                   - SRST_TIMER
 *                   - SRST_RTC
 *                   - SRST_DMA0
 *                   - SRST_GPIO
 *                   - SRST_WDG
 *                   - SRST_CRC
 *                   - SRST_EIO
 *                   - SRST_CAN0
 *                   - SRST_CAN1
 *                   - SRST_CTU
 *                   - SRST_ADC0
 *                   - SRST_ACMP0
 *                   - SRST_ANA_REG
 *                   - SRST_PWDT1
 * @param[in] active: active state
 *                   - ENABLE
 *                   - DISABLE
 * @return none
 */
void CKGEN_SoftReset(CKGEN_SoftResetType module, ACTION_Type active);

/*!
 * @brief Set the system clock source.
 *
 * @param[in] clockSource: system clock source, value can be
 *                        - SYSCLK_SRC_INTERNAL_OSC
 *                        - SYSCLK_SRC_PLL_OUTPUT
 *                        - SYSCLK_SRC_EXTERNAL_OSC
 * @return none
 */
void CKGEN_SetSysclkSrc(SYSTEM_ClockSourceType clockSource);

/*!
 * @brief Set the sysclck divider.
 *
 * @param[in] div: system clock divider set, value can be
 *                - SYSCLK_DIVIDER_1
 *                - SYSCLK_DIVIDER_2
 *                - SYSCLK_DIVIDER_3
 *                - SYSCLK_DIVIDER_4
 * @return none
 */
void CKGEN_SetSysclkDiv(SYSCLK_DividerType div);

/*!
 * @brief Set the APB clock divider.
 *
 * @param[in] div: apb clock divider set, value can be
 *                - APBCLK_DIVIDER_1
 *                - APBCLK_DIVIDER_2
 *                - APBCLK_DIVIDER_3
 *                - APBCLK_DIVIDER_4
 * @return none
 */
void CKGEN_SetAPBClockDivider(APBCLK_DividerType div);

/*!
 * @brief Enable/disable the XOSC monitor.
 *
 * @param[in] enable: enable state
 *                   - ENABLE
 *                   - DISABLE
 * @return none
 */
void CKGEN_EnableXOSCMonitor(ACTION_Type enable);

/*!
 * @brief Set the PLL reference.
 *
 * @param[in] ref: set PLL reference clock, value can be
 *                - PLL_REF_INTERNAL_OSC(8M)
 *                - PLL_REF_EXTERNAL_OSC
 * @return none
 */
void CKGEN_SetPLLReference(PLL_ReferenceType ref);

/*!
 * @brief Set the PLL previous divider.
 *
 * @param[in] div: set pll PREDIV, value can be
 *                - PLL_PREDIV_1
 *                - PLL_PREDIV_2
 *                - PLL_PREDIV_4
 * @return none
 */
void CKGEN_SetPllPrevDiv(PLL_PreDivType div);

/*!
 * @brief Set the PLL post divider.
 *
 * @param[in] div: set pll post-divider, value can be
 *                - PLL_POSDIV_1
 *                - PLL_POSDIV_2
 *                - PLL_POSDIV_4
 *                ...
 *                - PLL_POSDIV_62
 * @return none
 */
void CKGEN_SetPllPostDiv(PLL_PosDivType div);

/*!
 * @brief Set the PLL feedback divider.
 *
 * @param[in] div: set pll FBKDIV, value can be 0 to 255
 * @return none
 */
void CKGEN_SetPllFeedbackDiv(uint8_t div);

/*!
 * @brief Set the CAN function clock.
 *
 * @param[in] canIndex: CAN0/1
 * @param[in] sel: can clock source select, value can be
 *                - CAN_CLK_SEL_EXTERNAL_OSC
 *                - CAN_CLK_SEL_AHB
 * @return none
 */
void CKGEN_SetCANClock(uint8_t canIndex, CAN_ClockSelectType sel);

/*!
 * @brief Set the CAN time stamp clock divider.
 *
 * @param[in] canIndex: CAN0/1
 * @param[in] divider: CAN time clock divider, value can be
 *                - CAN_TIME_CLK_DIVIDER_8
 *                - CAN_TIME_CLK_DIVIDER_16
 *                - CAN_TIME_CLK_DIVIDER_24
 *                - CAN_TIME_CLK_DIVIDER_48
 * @return none
 */
void CKGEN_SetCANTimeDivider(uint8_t canIndex, CAN_TimeClockDividerType divider);

/*!
 * @brief Set the clock output.
 *
 * @param[in] enable: enable state
 *                   - ENABLE
 *                   - DISABLE
 * @param[in] sel: clock output select, value can be
 *                - CKGEN_CLKOUT_SEL_HSI
 *                - CKGEN_CLKOUT_SEL_HSE
 *                - CKGEN_CLKOUT_SEL_PLL
 *                - CKGEN_CLKOUT_SEL_SYS
 * @param[in] div: clock output divider, value can be
 *                - CKGEN_CLKOUT_DIV_1
 *                - CKGEN_CLKOUT_DIV_2
 *                - CKGEN_CLKOUT_DIV_4
 *                - CKGEN_CLKOUT_DIV_8
 * @return none
 */
void CKGEN_SetClockOut(ACTION_Type enable, CKGEN_ClkOutSelType sel, CKGEN_ClkOutDivType div);

/*!
 * @brief Set NMI IRQHandler callback function.
 *
 * @param[in] eventFunc: the pointer of the NMI call back function
 * @return none
 */
void NMI_SetCallback(const DeviceCallback_Type eventFunc);

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* _AC780X_CKGEN_H */

/* =============================================  EOF  ============================================== */
